MRAM Developer Day

August 5, 2019
Santa Clara, California


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Our Organizers

We wish to thank our organizers who are working to make this event a success.

Conference Chair

Barry Hoberman

Barry Hoberman

Independent Consultant

Barry Hoberman is an independent consultant focused on MRAM and other emerging memory technologies. He specializes in overcoming the challenges of moving from technology development to manufacturing. Involved with MRAM for over 10 years, he served as CEO/Chairman of startup Spin Transfer Technologies (STT), which is developing an advanced technology based on a proprietary writing technique. He also was CMO at previous startup Crocus Technology. He has been an MRAM spokesperson at many private, government, educational, and industry forums (including Flash Memory Summit), where he addressed market opportunities, manufacturing yields, and tradeoffs among performance, retention, and endurance.

He previously led semiconductor IP companies as CEO/founder at inSilicon (communications and I/O technology, acquired by Synopsys) and CEO at Virtual Silicon (embedded memory and libraries, acquired by Mosys). He holds a BSEE from MIT and over 20 US patents. He has over 35 years experience in the semiconductor industry with a focus on memory technology.


 

Dave Eggleston

Dave Eggleston

Principal of

Intuitive Cognition Consulting

Dave Eggleston is the owner and Principal of Intuitive Cognition Consulting, and he provides strategy and business development services to leading NVM and Storage clients. Dave's extensive background in Flash, MRAM, RRAM, and Storage is built on 30+ years of industry experience serving as VP of Embedded Memory at GLOBALFOUNDRIES, CEO of RRAM pioneer start-up Unity Semiconductor (acquired by Rambus), Director of Flash Systems Engineering at Micron, NVM Product Engineering manager at Sandisk, and NVM Engineer at AMD. Dave is frequently invited as a speaker at international conferences as an expert on emerging NVM technologies and their applications. He holds a BSEE degree from Duke University, a MSEE degree from Santa Clara University, and 25+ NVM related granted patents.

Tetsuo Endoh

Tetsuo Endoh

Professor/Director CIES

Tohoku University

Tetsuo Endoh joined Toshiba Co. in 1987 and was engaged in the R&D of NAND Memory. He became a lecturer at the Research Institute of Electrical Communication, Tohoku University in 1995. Now, he is director of the Center for Innovative Integrated Electronic Systems (CIES) and a Professor at the Department of Electrical Engineering, Graduate School of Engineering, Tohoku University. His current interests are novel 3D structured device technology, such as Vertical MOSFETs; high-density memory, such as SRAM, DRAM, 3D-NAND memory and STT-MRAM; and beyond-CMOS technology, such as spintronics-based non-volatile Logic for ultralow power systems such as mobile systems, AI systems and IoT systems. He is also interested in power-management technology, such as GaN on Si based power devices and power integrated circuits with low energy loss and low power consumption for automotive applications.


 

Shinobu Fujita

Shinobu Fujita

Chief Research Scientist

Toshiba

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Nilesh Gharia

Nilesh Gharia

CEO

NVMengines

Nilesh Gharia has 20+ years of experience in the semiconductor industry with a diverse background in semiconductor design and product development. During his time in Broadcom, the company was acquired by the industry giant, Avago. In addition to working in large corporations such as Broadcom, he was a part of the startup team at NetLogic Microsystems which went IPO and was later acquired by the former for $3.7B. Nilesh would later work in Virtual Silicon Technology after being the 1st Engineer at Lanstar Semiconductor, and was responsible for team development and product design. After 4 years from its inception, Lanstar Semiconductor went IPO. His expertise includes: startups, emerging memories, memory compiler development, MRAM technologies, semiconductor IP development, network processors, and team/project management. Nilesh holds a Masters in Electrical Engineering from the New Jersey Institute of Technology and has a portfolio 13 US issued patents.


 

Gouri	Sankar Kar

GouriSankar Kar

Program Director

IMEC

Gouri Sankar Kar received a Ph.D. degree in physics from the Indian Institute of Technology, Kharagpur, India, in 2002. In 2009, he joined imec, Leuven, Belgium, where he is currently ‎Distinguished Member of Technical Staff (DMTS). In this role, he defines the strategy and vision for RRAM, DRAM-MIMCAP and STT-MRAM programs both for stand-alone and embedded applications.

 

Jeff Lewis

Jeff Lewis

Sr VP Business Development

Spin Transfer Technologies

Jeff Lewis joins Spin Transfer Technologies as Senior Vice President of Business Development, bringing extensive experience in the semiconductor IP and EDA industries, focusing on licensing technologies in the memory sector. Most recently, Lewis was Senior Vice President of Business Development and Marketing at SuVolta, Inc., where he directed the company’s licensing, and customer and market engagement activities, including their strategic partnership and ultimate acquisition by Fujitsu. Prior to SuVolta, he served as Senior Vice President of Business Development and Marketing at Innovative Silicon. Additional leadership roles include President and CEO of CiraNova, an EDA software company acquired by Synopsys, and Vice President positions at FormFactor, Artisan Components and Compass Design Automation. Lewis earned an MBA from UC Berkeley Haas School of Business, and holds a Bachelor of Science degree in Electrical Engineering, and a Bachelor of Arts degree in Economics from UC Berkeley.


 

Ron Mertens

Ron Mertens

Editor-in-Chief

MRAM-info.com

Founder and editor of several emerging-technology knowledge hubs, including OLED-Info, Graphene-Info and MRAM-Info.

 

Daniel	Worledge

Daniel Worledge

Manager/MRAM

IBM

Dr. Worledge received a BA with a double major in Physics and Applied Mathematics from UC Berkeley in 1995, receiving the Department Scholar Award in physics and the Dorothea Klumpke Roberts Prize in mathematics. He then received a PhD in Applied Physics from Stanford University in 2000, with a thesis on spin-polarized tunneling in oxide ferromagnets, measuring the largest tunneling spin-polarization in (LaSr)MnO3 and the first negative tunneling spin-polarization in SrRuO3. After joining the Physical Sciences Department at the IBM T. J. Watson Research Center as a Post-doc in 2000, he became a Research Staff Member in 2001, inventing and developing Current-in-Plane Tunneling as a fast turn-around measurement method for magnetic tunnel junctions.

In 2003, Dr. Worledge became the manager of the MRAM Materials and Devices group, and in 2013 he became Senior Manager of MRAM. In 2014 he was promoted to Principle Research Staff Member and in 2015 to Distinguished Research Staff Member. He has worked on developing Toggle and then Spin Torque MRAM, including discovering perpendicular magnetic anisotropy in Ta|CoFeB|MgO, and leading the IBM team that developed perpendicular magnetic tunnel junctions and demonstrated the first integrated perpendicular spin torque MRAM, with ultra-low bit error rate. His current research interests include magnetic devices and their behavior at small dimensions, and new magnetic devices for logic applications. Dr. Worledge has received three IBM Outstanding Technical Achievement Awards and the IBM Research Client Award.


 

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Hiroaki (HK) Yoda

Senior Fellow

Toshiba Corporate R&D Center

Dr. Yoda got his Bachelor degree in Physics from Kyusyu University, Fukuoka, Japan, and M.S. degree in Electrical Engineering from Washington University, St. Louis, M.O., USA. Since 1999, he has been working at Toshiba corporate R&D center for HDD and MRAM applications. He has been working on magnetics technologies for about 30 years. He implemented the world 1st GMR based HDD heads and the world 1st demonstration of STT-writing on MTJs with perpendicular anisotropy. He got several awards including Nikkei BP grand award on GMR heads(1996), Kanto invention award on HDD read & write heads(2005), Ichimura Industrial award on HDD read & write heads(2005), and Japan national invention award on HDD read & write heads(2007).